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Memory Protection Unit

The Blackfin processor documentation details support for a “Memory Management Unit (MMU)”. While traditionally most people equate this with “virtual memory”, which the Blackfin processor does not support, many of the other features of a MMU are supported. We will use term Memory Protection Unit (MPU) specifically to avoid confusion with the standard MMU term.

The main features of the Blackfin MPU:

  • variable page sized granularity (1 KiB, 4 KiB, 1 MiB, 4 MiB)
  • distinction between supervisor and usermode access
  • read/write/execute permissions
  • cacheability of accesses

Like most MMU implementations, this only governs accesses made by the Blackfin core itself (Loads/Stores). There is no IOMMU/IOMPU to govern accesses made by peripherals, nor is there any DMAMMU/DMAMPU to govern accesses made by DMA.

Some other quick notes which we'll expand upon later: the Blackfin architecture does not have any hardware assistance in handling misses. It needs to implement everything in software. Nor does it have any dedicated exception states specifically for misses.

Terminology

The Blackfin documentation has some of its own terms to describe functionality that has common parallels. So let's glue the two worlds together.

Normally you would talk about Translation Lookaside Buffers (TLBs) which contain a fixed number of Page Table Entries (PTEs) which describe the virtual to physical address mappings as well as access permissions. The Blackfin processor has Cacheability Protection Lookaside Buffers (CPLBs) which contain a fixed number of CPLB descriptors (entries) which also describe memory mappings, but obviously omit the virtual aspect.

Since the Blackfin processor implements a Harvard architecture (separate pathways for instruction and data), the Blackfin MPU implements two Content-Addressable Memory blocks which form the foundation of the CPLBs. Other MMU implementations typically have a similar structure.

Functionality

Each CPLB entry consists of a pair of 32-bit Memory Mapped Registers (MMRs): an address ([DI]CPLB_ADDRx) and a description ([DI]CPLB_DATAx).

The ADDR MMR is a 32-bit address in the Blackfin memory map. It must be aligned to the page size declared in its corresponding DATA MMR. While the ADDR MMR may contain any address at all (even ones which have no valid memory behind it), entries describing the Blackfin MMR region itself are always ignored (so the top two megs of memory). Those regions are always covered by an implicit CPLB entry granting read/write access to supervisor mode only.

The DATA MMR is a 32-bit value that controls:

  • validity
  • entry locking
  • permissions
  • cache behavior
  • page size

Misses

The Blackfin processor only has one exception level where all exceptions go, and exceptions may not be nested. Thus the exception handler and any memory it uses must have dedicated CPLB entries specifically locked for it so that misses may be handled at any time.

There is no hardware table walking support for misses, nor is there a hardware assisted software table walking support, nor are there dedicated instructions to facilitate CPLB entry replacement.

Due to these limitations, handling misses can be expensive. This is why most systems will try and make sure it doesn't occur by covering everything with 4 MiB entries all the time. The downside is that this tends to grant full access to code running as supervisor (the OS) and to code running in user mode (userspace applications).