The Blackfin Processor On-Chip SDRAM Controller

The Blackfin Processor On-Chip SDRAM Controller

This Note is intended to help the user select and configure a suitable Synchronous Dynamic Random Access Memory (SDRAM) device to interface with ADI Blackfin processors.

The different factors involved in choosing the appropriate memory component depending on the Processor used will be discussed in this document. Additionally, some programming examples on how to configure the SDRAM controller will be shown.

Before an SDRAM device can be selected, the user needs to understand the features and specifications of the chosen Processor.

although this refers to the ADSP-BF533, the same concepts apply for all the Blackfin Processors with SDRAM Controllers, since the SDRAM Controller (SDC) functionality is the same for all parts (Where they are different, it will be noted).

SDRAM Specifications

There are several factors that need to be considered when selecting an SDRAM device to interface with a processors, which are common across all families:

Supported operating voltage
Maximum supported operating frequency
Maximum supported memory
I/O size and number of banks
Column Address Strobe (CAS) latency
Refresh rate
Burst length
Page size
Initialization sequence

All these characteristics are defined in the SDRAM device datasheet and must meet the specifications of the on-chip SDRAM controller of the processor being used in order to be able to gluelessly interface to it.

SDRAM Controller Features

These are the relevant ADSP-BF533 Processor on-chip SDRAM controller characteristics for choosing the appropriate memory device:

Specification	Requirement
Supported operating Voltage	3.3 and 2.5 V
Maximum supported operating Frequency	up to 133 MHz
Maximum supported memory	128 Mbytes (64 M x 16 bits)
Number of banks	4 banks
Column Address Strobe (CAS) latency	Programmable value: 2 or 3 system clock cycles (SCLK)
Refresh rate	Programmable value: 1 to 4095 system clock cycles (SCLK)
Burst Length	Burst length of 1
Page size	Programmable value to: 512, 1024 2048 or 4096 bytes
Initialization sequence	Programmable sequence: MRS → REF or REF → MRS

Calculating SDRAM Settings

This spreadsheet allows you to calculate EBIU SDRAM Register values based on timing specification taken from your SDRAM datasheet, and your target System Clock (SCLK).

EBIU SDRAM Registers
EBIU_SDGCTL
EBIU_SDBCTL
EBIU_SDRRC

This spreadsheet is assumed to be accurate, however there is no guarantee…

The latest version can be found here: http://ez.analog.com/docs/DOC-1441