Link ports allow the processor to connect to other processors or peripheral link ports using a simple communication protocol for high-speed parallel data transfer. This peripheral allows a variety of I/O peripheral interconnection schemes to I/O peripheral devices as well as co-processing and multiprocessing schemes. The ADSP-BF6xx processor has four link ports and each supports 8-bit wide data transfers at up to 83 MHz. The link ports are multiplexed as follows.

1. Link port 0 and 1 signals are multiplexed in GPIO ports A and B
2. Link port 2 and 3 signals are multiplexed in GPIO ports E and F

All Link Ports are identical in their design and have the following common features.

1. Bidirectional ports have eight data lines, an acknowledge line, and a clock line.
2. Provide high-speed, point-to-point data transfers to other processors, allowing differing types of interconnections between multiple DSPs
3. Pack data into 32-bit words. This data can be directly read by the processor or transferred via DMA to or from on-chip memory.
4. Support for 2-deep FIFO for transmit and 4-deep FIFO for receive.
5. Programmable clock and acknowledge based handshake mechanism for efficient communication.
6. Dedicated DMA engine.

     Character devices  --->
  │ │    <M> Blackfin General Purpose Timers char device interface        │ │
  │ │    < > Blackfin hardware CRC driver                                 │ │
  │ │    < > Blackfin SPORT driver for direct raw access                  │ │
  │ │    <M> Blackfin LINKPORT driver                                     │ │
  │ │    [ ] /dev/kmem virtual device support                             │ │
  │ │        Serial drivers  --->                                

root:/> ls /dev/linkport*

/dev/linkport0 /dev/linkport1 /dev/linkport2 /dev/linkport3

linkport_test will send data to linkport1, and receive data from linkport0, then verify the data.

root:/> linkport_test

linkport test passed.