@@ Line 73: / Line 73: @@
   typedef uint32_t sm_uint32_t;
   typedef void *sm_address_t;
+===== Cache policy =====
+One of the assumptions of the MCAPI/ICC protocol is that the payload buffer received on one core is located in the memory region managed(owned) by the other cores.
+Core 0 should set up write through CPLB entries for the memory region managed by core 1. So, The invalidate instruction on core 0 doesn’t flush dummy data in cache back to the MCAPI payload buffer sent by core 1 or drop unrelated data in the same cache line near the MCAPI payload boundary. What CPLB entries (WT/WB) are set up for the same memory region on core 1 doesn’t matter, because core 1 should flush the MCAPI payload buffer before sending.
+For example:
+^BF609 mem addr    ^ Owner ^ Core0 cache ^ Core1 cache ^
+|0~0x3FFFFF        | Core0 | WB          | WT |
+|0x400000~0x800000 | Core1 | WT          | WB |
 ===== Atomic access =====
@@ Line 140: / Line 151: @@
 **Message queues** are circular buffers containing SM_MSGQ_LEN fixed size messages.
 <code>
-  typedef struct sm_msg {
-        sm_uint16_t dst_ep;
-        sm_uint16_t src_ep;
-        sm_uint32_t type;
-        sm_address_t payload;
-        sm_uint32_t length ;
-  } sm_msg_t;
   typedef struct {
     sm_atomic_t sent;
@@ Line 436: / Line 438: @@
 </code>
-The ID of a shared resource is unique among all kinds of resources. The supper 4 bits indicate the type of the shared resource, while the rest 12 bits is the index in the given type group. There are at most 16 (2^4) types and only 5 is defined yet. For each type, there could be at most 4096 (2^12) individual resources.
+The ID of a shared resource is unique among all kinds of resources. The supper 4 bits indicate the type of the shared resource, while the rest 12 bits is the index in the given type group. There are at most 16 (2^4) types and only 5 is defined yet. For each type, there could be at most 4096 (2^12) individual resources. The SM_RES_MGR message use payload to pass resouce ID, and use length to point to a 32-bit resouce description data address if resouce type is RESMGR_TYPE_PERIPHERAL.
 <code>
 // resource types
@@ Line 462: / Line 465: @@
-Resouce description data should be put in the payload buffer of the message in following format.
+Resource description data address should be put in the length of the message in following format.
 <code>
 typedef struct {
-  uint8 label[32];			// owner name
+  uint8_t label[32];			        // resource device owner name
-  uint16 count;				// resource number in next array
+  uint16_t count;				// resource number in next array
-  uint16 resources[1];			// first element of the resource ID array
+  uint32_t resources_array;			// address of the resource ID array
 } resources_t;
 </code>
-The generic map of the peripherals, GPIOs, system IRQs and DMA channels to their ID should be defined for each arch. The resource sequence in the HRM can be one reference for the generic map.
+Resource manager APIs declaration:
+<code>
+int sm_request_resource(uint32_t dst_cpu, uint32_t resource_id, resources_t *data)
+int sm_free_resource(uint32_t dst_cpu, uint32_t resource_id, resources_t *data)
+</code>
-=== Specifics for BF561 ===
+==== peripherals type ====
+For peripherals type, the peripheral name and list is passed by resouce description data.
+=== example to request/free peripherals type ===
-^Peripheral ID	^Peripheral in bf561 HRM^
+<code>
-|0		|SPI0|
-|1		|PPI0|
+unsigned short bfin_peripheral_list[] = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0};
-|2		|PPI1|
+resources_t bfin_peri_res = {
-|3		|SPORT0|
+        .label = "bfin-spi1",
-|4		|SPORT1|
+};
-|5		|UART0|
-|6		|TIMER0|
+       bfin_peri_res.count = 3;
+        bfin_peri_res.resources_array = (uint32_t)bfin_peripheral_list;
+        COREB_DEBUG(1, "request resource id %s\n", bfin_peri_res.label);
+        ret = sm_request_resource(EP_RESMGR_SERVICE, RESMGR_ID(RESMGR_TYPE_PERIPHERAL, 0), &bfin_peri_res);
+        if (ret) {
+                COREB_DEBUG(1, "request peri resource failed\n");
+        }
+        ret = sm_free_resource(EP_RESMGR_SERVICE, RESMGR_ID(RESMGR_TYPE_PERIPHERAL, 0), &bfin_peri_res);
+        if (ret) {
+                COREB_DEBUG(1, "free peri resource failed\n");
+        }
+</code>
+==== GPIO, IRQ and DMA type ====
+The generic map of the GPIOs, system IRQs and DMA channels to their ID should be defined for each arch. The resource sequence in the HRM can be one reference for the generic map.
+=== Specifics for BF561 ===
 ^GPIO ID	^GPIO in bf561 HRM  ^
@@ Line 595: / Line 623: @@
 |35		|IMDMA_MEM_STREAM1_SRC|
+=== Specifics for BF609 ===
-=== An example to use resource manager protocol ===
+^GPIO ID	^GPIO in bf609 HRM  ^
+|0		|GPIO0|
+|1		|GPIO1|
+|...		|...|
+|112		|GPIO112|
+^System IRQ ID	^System IRQ in b609 HRM^
+|0 |IRQ_SEC_ERR|
+|1 |IRQ_CGU_EVT|
+|2 |IRQ_WATCH0|
+|3 |IRQ_WATCH1|
+|4 |IRQ_L2CTL0_ECC_ERR|
+|5 |IRQ_L2CTL0_ECC_WARN|
+|6 |IRQ_C0_DBL_FAULT|
+|7 |IRQ_C1_DBL_FAULT|
+|8 |IRQ_C0_HW_ERR|
+|9 |IRQ_C1_HW_ERR|
+|10 |IRQ_C0_NMI_L1_PARITY_ERR|
+|11 |IRQ_C1_NMI_L1_PARITY_ERR|
+|12 |IRQ_TIMER0|
+|13 |IRQ_TIMER1|
+|14 |IRQ_TIMER2|
+|15 |IRQ_TIMER3|
+|16 |IRQ_TIMER4|
+|17 |IRQ_TIMER5|
+|18 |IRQ_TIMER6|
+|19 |IRQ_TIMER7|
+|20 |IRQ_TIMER_STAT|
+|21 |IRQ_PINT0|
+|22 |IRQ_PINT1|
+|23 |IRQ_PINT2|
+|24 |IRQ_PINT3|
+|25 |IRQ_PINT4|
+|26 |IRQ_PINT5|
+|27 |IRQ_CNT|
+|28 |IRQ_PWM0_TRIP|
+|29 |IRQ_PWM0_SYNC|
+|30 |IRQ_PWM1_TRIP|
+|31 |IRQ_PWM1_SYNC|
+|32 |IRQ_TWI0|
+|33 |IRQ_TWI1|
+|34 |IRQ_SOFT0|
+|35 |IRQ_SOFT1|
+|36 |IRQ_SOFT2|
+|37 |IRQ_SOFT3|
+|38 |IRQ_ACM_EVT_MISS|
+|39 |IRQ_ACM_EVT_COMPLETE|
+|40 |IRQ_CAN0_RX|
+|41 |IRQ_CAN0_TX|
+|42 |IRQ_CAN0_STAT|
+|43 |IRQ_SPORT0_TX|
+|44 |IRQ_SPORT0_TX_STAT|
+|45 |IRQ_SPORT0_RX|
+|46 |IRQ_SPORT0_RX_STAT|
+|47 |IRQ_SPORT1_TX|
+|48 |IRQ_SPORT1_TX_STAT|
+|49 |IRQ_SPORT1_RX|
+|50 |IRQ_SPORT1_RX_STAT|
+|51 |IRQ_SPORT2_TX|
+|52 |IRQ_SPORT2_TX_STAT|
+|53 |IRQ_SPORT2_RX|
+|54 |IRQ_SPORT2_RX_STAT|
+|55 |IRQ_SPI0_TX|
+|56 |IRQ_SPI0_RX|
+|57 |IRQ_SPI0_STAT|
+|58 |IRQ_SPI1_TX|
+|59 |IRQ_SPI1_RX|
+|60 |IRQ_SPI1_STAT|
+|61 |IRQ_RSI|
+|62 |IRQ_RSI_INT0|
+|63 |IRQ_RSI_INT1|
+|64 |IRQ_SDU|
+|65 |DMA12 Data Reserved |
+|66 |Reserved |
+|67 |Reserved |
+|68 |IRQ_EMAC0_STAT|
+|69 |EMAC0 Power Reserved |
+|70 |IRQ_EMAC1_STAT|
+|71 |EMAC1 Power Reserved |
+|72 |IRQ_LP0|
+|73 |IRQ_LP0_STAT|
+|74 |IRQ_LP1|
+|75 |IRQ_LP1_STAT|
+|76 |IRQ_LP2|
+|77 |IRQ_LP2_STAT|
+|78 |IRQ_LP3|
+|79 |IRQ_LP3_STAT|
+|80 |IRQ_UART0_TX|
+|81 |IRQ_UART0_RX|
+|82 |IRQ_UART0_STAT|
+|83 |IRQ_UART1_TX|
+|84 |IRQ_UART1_RX|
+|85 |IRQ_UART1_STAT|
+|86 |IRQ_MDMA0_SRC_CRC0|
+|87 |IRQ_MDMA0_DEST_CRC0/ IRQ_MDMAS0|
+|88 |IRQ_CRC0_DCNTEXP|
+|89 |IRQ_CRC0_ERR|
+|90 |IRQ_MDMA1_SRC_CRC1|
+|91 |IRQ_MDMA1_DEST_CRC1/IRQ_MDMAS1 |
+|92 |IRQ_CRC1_DCNTEXP|
+|93 |IRQ_CRC1_ERR|
+|94 |IRQ_MDMA2_SRC|
+|95 |IRQ_MDMA2_DEST/IRQ_MDMAS2|
+|96 |IRQ_MDMA3_SRC|
+|97 |IRQ_MDMA3_DEST/IRQ_MDMAS3 |
+|98 |IRQ_EPPI0_CH0|
+|99 |IRQ_EPPI0_CH1|
+|100 |IRQ_EPPI0_STAT|
+|101 |IRQ_EPPI2_CH0|
+|102 |IRQ_EPPI2_CH1|
+|103 |IRQ_EPPI2_STAT|
+|104 |IRQ_EPPI1_CH0|
+|105 |IRQ_EPPI1_CH1|
+|106 |IRQ_EPPI1_STAT|
+|107 |IRQ_PIXC_CH0|
+|108 |IRQ_PIXC_CH1|
+|109 |IRQ_PIXC_CH2|
+|110 |IRQ_PIXC_STAT|
+|111 |IRQ_PVP_CPDOB|
+|112 |IRQ_PVP_CPDOC|
+|113 |IRQ_PVP_CPSTAT|
+|114 |IRQ_PVP_CPCI|
+|115 |IRQ_PVP_STAT0|
+|116 |IRQ_PVP_MPDO|
+|117 |IRQ_PVP_MPDI|
+|118 |IRQ_PVP_MPSTAT|
+|119 |IRQ_PVP_MPCI|
+|120 |IRQ_PVP_CPDOA|
+|121 |IRQ_PVP_STAT1|
+|122 |IRQ_USB_STAT|
+|123 |IRQ_USB_DMA|
+|124 |IRQ_TRU_INT0|
+|125 |IRQ_TRU_INT1|
+|126 |IRQ_TRU_INT2|
+|127 |IRQ_TRU_INT3|
+|128 |IRQ_DMAC0_ERROR|
+|129 |IRQ_CGU0_ERROR|
+|130 |Reserved |
+|131 |IRQ_DPM|
+|132 |Reserved |
+|133 |IRQ_SWU0|
+|134 |IRQ_SWU1|
+|135 |IRQ_SWU2|
+|136 |IRQ_SWU3|
+|137 |IRQ_SWU4|
+|138 |IRQ_SWU5|
+|139 |IRQ_SWU6|
+^DMA ID		^DMA in bf609 HRM^
+|0 |CH_SPORT0_TX|
+|1 |CH_SPORT0_RX|
+|2 |CH_SPORT1_TX|
+|3 |CH_SPORT1_RX|
+|4 |CH_SPORT2_TX|
+|5 |CH_SPORT2_RX|
+|6 |CH_SPI0_TX|
+|7 |CH_SPI0_RX|
+|8 |CH_SPI1_TX|
+|9 |CH_SPI1_RX|
+|10 |CH_RSI|
+|11 |CH_SDU|
+|13 |CH_LP0|
+|14 |CH_LP1|
+|15 |CH_LP2|
+|16 |CH_LP3|
+|17 |CH_UART0_TX|
+|18 |CH_UART0_RX|
+|19 |CH_UART1_TX|
+|20 |CH_UART1_RX|
+|21 |CH_MEM_STREAM0_SRC_CRC0/CH_MEM_STREAM0_SRC|
+|22 |CH_MEM_STREAM0_DEST_CRC0/CH_MEM_STREAM0_DEST|
+|23 |CH_MEM_STREAM1_SRC_CRC1/CH_MEM_STREAM1_SRC|
+|24 |CH_MEM_STREAM1_DEST_CRC1/CH_MEM_STREAM1_DEST|
+|25 |CH_MEM_STREAM2_SRC|
+|26 |CH_MEM_STREAM2_DEST|
+|27 |CH_MEM_STREAM3_SRC|
+|28 |CH_MEM_STREAM3_DEST|
+|29 |CH_EPPI0_CH0|
+|30 |CH_EPPI0_CH1|
+|31 |CH_EPPI2_CH0|
+|32 |CH_EPPI2_CH1|
+|33 |CH_EPPI1_CH0|
+|34 |CH_EPPI1_CH1|
+|35 |CH_PIXC_CH0|
+|36 |CH_PIXC_CH1|
+|37 |CH_PIXC_CH2|
+|38 |CH_PVP_CPDOB|
+|39 |CH_PVP_CPDOC|
+|40 |CH_PVP_CPSTAT|
+|41 |CH_PVP_CPCI|
+|42 |CH_PVP_MPDO|
+|43 |CH_PVP_MPDI|
+|44 |CH_PVP_MPSTAT|
+|45 |CH_PVP_MPCI|
+|46 |CH_PVP_CPDOA|
+=== An example request/free other resource type ===
 <code>
-sm_msg_t res_request;
-uint8 res_payload[100];
-resources_t *resp = res_payload;
-strncpy(resp->;label, "test owner", 31);
+ret = sm_request_resource(EP_RESMGR_SERVICE, RESMGR_ID(RESMGR_TYPE_GPIO, 40), 0);
-resp->count = 3;
+if (ret)
-resp->resource[0] = RESMGR_ID(RESMGR_TYPE_GPIO, PF0);
+    COREB_DEBUG(1, "request resource failed\n");
-resp-&gt;resource[1] = RESMGR_ID(RESMGR_TYPE_GPIO, PF4);
-resp-&gt;resource[2] = RESMGR_ID(RESMGR_TYPE_SYS_IRQ, PF0_PF15_A);
+ret = sm_request_resource(EP_RESMGR_SERVICE, RESMGR_ID(RESMGR_TYPE_SYS_IRQ, 52), 0);
+if (ret)
+    COREB_DEBUG(1, &quot;request resource failed\n");
+ret = sm_request_resource(EP_RESMGR_SERVICE, RESMGR_ID(RESMGR_TYPE_DMA, 20), 0);
+if (ret)
+    COREB_DEBUG(1, &quot;request resource failed\n");
-res_request.des_ep = EP_RESMGR_SERVICE;
+sm_free_resource(EP_RESMGR_SERVICE, RESMGR_ID(RESMGR_TYPE_GPIO, 40), 0);
-res_request.src_ep = any_available_local_ep; // should be > EP_RES_MGR_MAX
+sm_free_resource(EP_RESMGR_SERVICE, RESMGR_ID(RESMGR_TYPE_SYS_IRQ, 52), 0);
-res_request.type = SM_MSG_TYPE(SM_RES_MGR_REQUEST, SP_RES_MANAGER);
+sm_free_resource(EP_RESMGR_SERVICE, RESMGR_ID(RESMGR_TYPE_DMA, 20), 0);
-res_request.payload = res_payload;
-res_request.len = sizeof(struct resource_t)
-        + sizeof(uint16) * (resp->count - 1) ;
 </code>

Differences