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Blackfin Basics

Introduction

Intel and Analog Devices Inc. (ADI) jointly developed the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then Intel has put this in its cell phone chipsets, (and then sold that business to Marvell), and ADI has put this core into it's Blackfin processor family of devices, which include over 15 different devices/speed grade options, including a dual core chip where each core can run at 600MHz, and it's own cell phone chipsets (which it sold to MediaTek.

This document will focus on ADI's ADSP‑BF533 Blackfin device, which can be found on the BF533 STAMP platform. The MSA core, found in the BF533, has the advantages of a clean, orthogonal, RISC-like microprocessor instruction set. It combines a dual‑MAC (Multiply/Accumulate), state‑of‑the‑art signal processing engine and single-instruction, multiple‑data (SIMD) multimedia capabilities into a single instruction-set architecture. Since the core was recently developed, it takes advantage of the experience that processor architects have gained over the past 25 years and attempts to meet the needs of DSP, microcontroller, and multimedia processing algorithms that are popular today.

The DSP features include one instruction port and two separate data ports mapped to a unified 4GB memory space; two 16-bit, single-cycle throughput multipliers; two 40-bit split data ALUs; two 32‑bit pointer ALUs with support for circular and bit-reversed addressing; two loop counters that allow nested, zero overhead looping; and hardware support for on-the-fly saturation and clipping.

The microcontroller features include arbitrary bit manipulation; mixed 16-bit and 32-bit instruction encoding for high code density; memory protection; stack pointers and scratch SRAM for context switching; flexible power management; and an extensible, nested, and prioritized interrupt controller for real-time control.

The multimedia features include four auxiliary 8-bit data ALUs and a rich set of alignment‑independent, packed byte operation instructions. These instructions enable the acceleration of fundamental operations associated with video and imaging based applications.

Blackfin Peripherals

Depending on the Blackfin derivative, it contains several on-chip peripherals. These include:

Feature BF522 BF525 BF527 BF531 BF532 BF533 BF534 BF535 BF536 BF537 BF538 BF542 BF544 BF548 BF549 BF561
ATAPI (PATA) 1 1 1
CAN 1 1 1 1 1 2 2 2
Code Security
Ethernet MAC 1 1
GPIOs 48 48 48 16 16 16 48 48 48 54 152 152 152 152
GP Timers 8 8 8 3 3 3 8 8 8 3 8 11 8 8
Host DMA
MXVR (MOST) 1
PCI 1
PPI 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2
RTC
SD/SDIO 1 1 1
SPI 1 1 1 1 1 1 1 1 1 1 3 2 2 3 3
SPORTs 2 2 2 2 2 2 2 2 2 2 4 3 3 4 4 2
TWI 1 1 1 1 1 1 2 1 2 2 2
UARTs 2 2 2 1 1 1 2 1 2 2 3 3 3 4 4 1
USB 1 1 1 1 1 1
Watchdog Timers 1 1 1 1 1 1 1 1 1 1 1 1 1 1

These peripherals are connected to the core via several high bandwidth buses, as shown below:

Figure 2-1. Processor Block Diagram

Parallel Peripheral Interface (PPI)

The processor provides a Parallel Peripheral Interface (PPI) that can connect directly to parallel A/D and D/A converters, ITU-R 601/656 video encoders and decoders, and other general-purpose peripherals. Three distinct ITU-R 656 modes are supported:

  • Active Video Only
  • Vertical Blanking Only
  • Entire Field

General-purpose modes of the PPI are provided to suit a wide variety of data capture and transmission applications. These modes are divided into four main categories:

  • Data Receive with Internally Generated Frame Syncs
  • Data Receive with Externally Generated Frame Syncs
  • Data Transmit with Internally Generated Frame Syncs
  • Data Transmit with Externally Generated Frame Syncs

Serial Ports (SPORTs)

The processor incorporates two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support these features:

  • I2S capable operation
  • Bidirectional operation - Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I2S stereo audio.
  • Buffered (eight-deep) transmit and receive ports
  • Clocking - Each transmit and receive port can either use an external serial clock or generate its own.
  • Word length - Each SPORT supports serial data words from 3 to 32 bits in length.
  • Framing - Each transmit and receive port can run with or without frame sync signals.
  • Companding in hardware - Each SPORT can perform A-law or µ-law companding according to ITU G.711.
  • DMA operations with single-cycle overhead
  • Interrupts - Each transmit and receive port can generate an interrupt upon completing the transfer of data.
  • Multichannel capability - Each SPORT supports 128 channels out of a 1024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards.

Serial Peripheral Interface (SPI) Port

The processor has an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices.

The SPI interface uses three pins for transferring data: two data pins and a clock pin. An SPI chip select input pin lets other SPI devices select the processor, and seven SPI chip select output pins let the processor select other SPI devices. Using these pins, the SPI port provides a full‑duplex, synchronous serial interface, which supports both master and slave modes and multi‑master environments.

The SPI port's baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller, configurable to support either transmit or receive datastreams.

Timers

There are four general-purpose programmable timer units in the processor. Three timers have an external pin that can be configured either as a Pulse Width Modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths of external events.

These timer units can be synchronized to an external clock input connected to the PF1 pin, an external clock input to the PPI_CLK pin, or to the internal SCLK.

The timers can generate interrupts to the processor core, either to the processor clock or to a count of external signals. In addition to the three general-purpose programmable timers, a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.

Universal Asynchronous Receiver Transmitter (UART) Port

The processor provides a half-duplex UART port. The UART port supports two modes of operation:

  • Programmed I/O - The processor sends or receives data by writing or reading I/O‑mapped UART registers.
  • Direct Memory Access (DMA) - The DMA controller transfers both transmit and receive data.

Real-Time Clock (RTC)

The processor's Real-Time Clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the processor. The RTC peripheral has dedicated power supply pins, so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options. The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. Like the other peripherals, the RTC can wake up the processor from Sleep mode or Deep Sleep mode.

Watchdog Timer

The processor includes a 32-bit timer that can be used to implement a software watchdog function. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value.

Programmable Flags

The processor has 16 bidirectional programmable flag (PF) or general-purpose I/O pins PF[15:0]. Each pin can be individually configured using the flag control, status, and interrupt registers.

  • Flag Direction Control register - Specifies the direction of each individual PFx pin as input or output.
  • Flag Control and Status registers -The processor employs a “write-1-to-modify” mechanism that allows any combination of individual flags to be modified in a single instruction, without affecting the level of any other flags.
  • Flag Interrupt Mask registers - The two Flag Interrupt Mask registers allow each individual PFx pin to function as an interrupt to the processor. The PFx pins defined as inputs can be configured to generate hardware interrupts, while output PFx pins can be triggered by software interrupts.
  • Flag Interrupt Sensitivity registers - The two Flag Interrupt Sensitivity registers specify whether individual PFx pins are level- or edge‑sensitive and specify if edge‑sensitive whether just the rising edge or both the rising and falling edges of the signal are significant.

Memory Layout

The Blackfin processor architecture structures memory as a single, unified 4Gbyte address space using 32‑bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. Level 1 (L1) memories are located on the chip and are faster than the Level 2 (L2) off-chip memories. The memory map of the ADSP-BF533 is given in figure 2‑1. MMR is an acronym for Memory Mapped Register.

Figure 2-2. ADSP-BF533 Memory Map

Internal Memory

The processor has three blocks of on-chip memory that provide high bandwidth access to the core. This memory is accessed at full processor speed:

  • L1 instruction memory - This consists of SRAM and a 4‑way set‑associative cache.
  • L1 data memory - This consists of SRAM and/or a 2-way set-associative cache.
  • L1 scratchpad RAM - This memory is only accessible as data SRAM and cannot be configured as cache memory.

External Memory

External (off-chip) memory is accessed via the External Bus Interface Unit (EBIU). This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) and as many as four banks of asynchronous memory devices including flash memory, EPROM, ROM, SRAM, and memory-mapped I/O devices.

The PC133-compliant SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM.

The asynchronous memory controller can be programmed to control up to four banks of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated with 1M byte of memory.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. Control registers for on-chip I/O devices are mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks: one contains the control MMRs for all core functions and the other contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in Supervisor mode. They appear as reserved space to on-chip peripherals.

Alignment

Nonaligned memory operations are not supported. A nonaligned memory reference generates a Misaligned Access exception event or Bus error. This is caused by either a load or store instruction which is accessing 32-bit data on non 32-bit aligned memory addresses, or 16-bit data on non 16 bit addresses. For example, the assembly code:

    R0 = [P0];
    R1 = W[P1];
    R2 = B[P2];

May work or cause bus errors depending on the values of P0 or P1, since the load address must be aligned to the memory access. R0 is doing a 32-bit access, R1 is a 16-bit access, and R2 is a 8-bit access.

  • if P0 is a 32-bit aligned address (0, 4, 8, 12 …) it will work. Non-aligned addresses (1, 2, 3, 5, 6, 7 …) will fail.
  • if P1 is a 16-bit aligned address (0, 2, 4, 6, …) it will work. Non-aligned addresses (1, 3, 5, 7, 9, 11 …) will fail
  • if P2 is any value, it will work.

To solve these types of problems, look at how to debug applications.

Boot Configurations

The internal boot ROM includes a small boot kernel that can either be bypassed or used to load user code from an external memory device after a reset. For more information on the topic, see the sections dedicated to the bootrom.

blackfin.uclinux.org Website

The website http://blackfin.uclinux.org is a central repository where developers and testers from the open source community can collaborate on projects relating to Blackfin devices. This website allows users to post software and documentation, discuss issues relating to the various projects, post bugs, and offer suggestions to project developers.

There are several projects on this website dedicated to the development of open source hardware and software tools for Blackfin devices. These projects include the STAMP development board, the GNU GCC tool chain, and the uClinux kernel.

A good place to get started on the Blackfin/uClinux website is the Project Tree tab. From here you can browse all the project categories and associated projects. Clicking on a particular project's link brings up a set of tabs for that particular project. These tabs allow you to view various aspects of the project such as the discussion forums, news relating to the project, and files associated with the project.

Posting a Question

Under each project's Forums tab there is usually a public help forum. This is a good place to look for answers to questions you may have. If your question is not answered here you may post a new thread and wait for a response. You need to be a registered user to post to a forum. You may register for a new account on the Blackfin/uClinux site by clicking on the New Account link.

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