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Silicon Anomaly Support for the Blackfin processor

An anomaly is normally defined as any occurrence or object that is strange, unusual, or unique. In the case of Blackfin processor - it means a discrepancy or deviation from the published documentation.

These anomalies represent the currently known issues between various revisions of the Blackfin processor and the functionality specified in the datasheet(s) or the Hardware Reference book(s). The authoritative source for which processor and version the anomaly affects are listed on the Analog Devices Web site - at the Blackfin Anomaly page.

Silicon anomalies can lead to erratic behaviors and consequently lead to instability in a hardware system. This document outlines all the silicon anomaly workarounds relevant to any open source software, targeting the Blackfin processors. Silicon anomalies that cannot be worked around in software are highlighted so that the developer can be aware of them and take appropriate action to prevent them from occurring at a system level.

It is up to YOU to review this list, and ensure that all workarounds which you need are enabled, and working properly. While we take best efforts in making things work, and attempt to do our best - you are still responsible for your product. When making a product which uses the gcc toolchain, but does not use U-Boot or the Linux kernel - only you can be responsible to make sure that your driver implements the necessary workarounds.

While anomaly workarounds exist in the toolchain, U-Boot and in the Linux Kernel - they only will work, if you use them properly. For example, the peripheral anomalies have workarounds in them in the peripheral device drivers. It is up to you to ensure that you use the existing device drivers. If you go changing the device driver, or write your own - it is your responsibility to ensure that you implement one of the suggested anomaly workaround methods from the silicon anomaly sheet.

All workarounds which can affect Linux userspace code - are all fixed in the toolchain - so no changes to userspace applications or libraries source is needed.

Supported Parts

These are managed in the toolchain repository, for each anomaly sheet that is on the Analog Devices Web site.

This list is autogenerated - DO NOT EDIT

Generic Extended List Possible Revisions
BF518(F) any of ADSP-BF512/BF514/BF516 or BF518 0.0, 0.1
BF526(C) any of ADSP-BF522/BF524 or BF526 0.0, 0.1
BF527(C) any of ADSP-BF523/BF525 or BF527 0.0, 0.1, 0.2
BF533 any of ADSP-BF531/BF532 or BF533 0.3, 0.4, 0.5, 0.6
BF537 any of ADSP-BF534/BF536 or BF537 0.2, 0.3, 0.4
BF538 any of ADSP-BF538 or BF538F 0.4, 0.5
BF539 any of ADSP-BF539 or BF539F 0.4, 0.5
BF548 any of ADSP-BF542/BF544/BF547/BF548/BF549/BF542M/BF544M/BF547M/BF548M or BF549M 0.2, 0.3M
BF561 ADSP-BF561 0.3, 0.5, 0.6

If you are using a revision not included on this list - it is not going to work with any of the open source tools or kernels - If you want to understand why - please review all the issues below this list.

BF518

file: proc-defs/header-frags/bf518/anomaly.h

scm failed with exit code 1:
file does not exist in git

file: proc-defs/header-frags/bf518/anomaly.h

scm failed with exit code 1:
file does not exist in git

BF527

file: proc-defs/header-frags/bf527/anomaly.h

scm failed with exit code 1:
file does not exist in git

file: proc-defs/header-frags/bf527/anomaly.h

scm failed with exit code 1:
file does not exist in git

BF533

file: proc-defs/header-frags/bf533/anomaly.h

scm failed with exit code 1:
file does not exist in git

file: proc-defs/header-frags/bf533/anomaly.h

scm failed with exit code 1:
file does not exist in git

BF537

file: proc-defs/header-frags/bf537/anomaly.h

scm failed with exit code 1:
file does not exist in git

file: proc-defs/header-frags/bf537/anomaly.h

scm failed with exit code 1:
file does not exist in git

BF538

file: proc-defs/header-frags/bf538/anomaly.h

scm failed with exit code 1:
file does not exist in git

file: proc-defs/header-frags/bf538/anomaly.h

scm failed with exit code 1:
file does not exist in git

BF548

file: proc-defs/header-frags/bf548/anomaly.h

scm failed with exit code 1:
file does not exist in git

file: proc-defs/header-frags/bf548/anomaly.h

scm failed with exit code 1:
file does not exist in git

BF561

file: proc-defs/header-frags/bf561/anomaly.h

scm failed with exit code 1:
file does not exist in git

file: proc-defs/header-frags/bf561/anomaly.h

scm failed with exit code 1:
file does not exist in git

If you believe these are out of date - please let us know in the toolchain forums

Working Around Anomalies

Since looking up pdfs isn't the easiest way to manage a complex application, there are anomaly header files which include define to allow you to work around these issues dynamically in your code. These look like:

file: proc-defs/header-frags/bf518/anomaly.h

scm failed with exit code 1:
file does not exist in git

or ones that depend on the silicon version:

file: proc-defs/header-frags/bf533/anomaly.h

scm failed with exit code 1:
file does not exist in git

Where __SILICON_REVISION__ is a compiler set directive, based on the flag which you passed to the -mcpu= command line option. This allows you to use these either as a C preprocessor (with ifdefs) or in normal C/C++ code like:

file: arch/blackfin/kernel/setup.c

scm failed with exit code 1:
file does not exist in git

An example of the -mcpu= command line would be:

rgetz@imhotep:~/blackfin/trunk/uClinux-dist> bfin-uclinux-gcc -mcpu=bf537-0.2 -g -O2  hello.c

This will enable any toolchain workarounds for the 0.2 version of the ADSP-BF537 processor, and set the __SILICON_REVISION__ to 2.

If silicon version is specified to be none, then no errata workarounds are enabled. If silicon version is specified to any then this will enable all workarounds for the target processor. All developers should ensure the correct silicon part/revision is specified on the command line when invoking a particular tool.

Anomalies & Supported Workarounds

This list is autogenerated - DO NOT EDIT

Anomaly Summary Blackfin Workaround in
ID affected Hardware Toolchain U-Boot Linux Kernel
05000074 Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF533-0.[0-6]
BF537-0.[0-3]
BF538-0.[0-5]
BF539-0.[0-5]
BF548-0.{0,1,2,3M}
BF561-0.[0-5]
05000099 UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time BF533-0.[0-4]
BF561-0.[0-3]
05000105 Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match BF533-0.[3-6]
05000119 DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops BF52[67]
BF533-0.[0-6]
BF537-0.[0-3]
BF538-0.[0-5]
BF539-0.[0-5]
BF548-0.{0,1,2,3M}
05000120 Testset instructions restricted to 32-bit aligned memory locations BF561-0.[0-5]
05000122 Rx.H Cannot Be Used to Access 16-bit System MMR Registers BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF533-0.[0-6]
BF537-0.[0-3]
BF538-0.[0-5]
BF539-0.[0-5]
BF548-0.{0,1,2,3M}
BF561-0.[0-5]
05000127 Signbits instruction not functional under certain conditions BF561-0.[0-5]
05000149 IMDMA S1/D1 channel may stall BF561-0.[0-6]
05000156 Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs BF561-0.[0-3]
05000158 Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) BF533-0.[0-4]
05000166 PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits BF533-0.[0-6]
BF538-0.[0-5]
BF539-0.[0-5]
BF561-0.[0-6]
05000167 Turning SPORTs on while External Frame Sync Is Active May Corrupt Data BF533-0.[0-6]
BF561-0.[0-6]
05000168 SDRAM auto-refresh and subsequent Power Ups BF533-0.[0-2]
BF561-0.[0-3]
05000169 DATA CPLB page miss can result in lost write-through cache data writes BF533-0.[0-2]
BF561-0.[0-3]
05000171 Boot-ROM code modifies SICA_IWRx wakeup registers BF561-0.[0-3]
05000174 Cache Fill Buffer Data lost BF533-0.[0-2]
BF561-0.[0-3]
05000175 Overlapping Sequencer and Memory Stalls BF533-0.[0-2]
BF561-0.[0-3]
05000176 Multiplication of (-1) by (-1) followed by an accumulator saturation BF533-0.[0-2]
BF561-0.[0-3]
05000179 PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes BF533-0.[0-4]
BF538-0.[1-5]
BF539-0.[0-5]
BF561-0.[0-3]
05000180 PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs BF533-0.[0-6]
BF537-0.[0-3]
BF538-0.[0-5]
BF539-0.[0-5]
BF561-0.[0-5]
05000181 Disabling the PPI resets the PPI configuration registers BF533-0.[0-2]
BF561-0.[0-3]
05000182 IMDMA does not operate to full speed for 600MHz and higher devices BF561-0.[0-6]
05000183 Timer Pin Limitations for PPI TX Modes with External Frame Syncs BF533-0.[0-3]
05000184 Timer Pin limitations for PPI TX Modes with External Frame Syncs BF561-0.[0-3]
05000185 PPI TX Mode with 2 External Frame Syncs BF533-0.[0-2]
BF561-0.[0-3]
05000186 PPI packing with Data Length greater than 8 bits (not a meaningful mode) BF561-0.[0-3]
05000187 IMDMA Corrupted Data after a Halt BF561-0.[0-6]
05000188 IMDMA Restrictions on Descriptor and Buffer Placement in Memory BF561-0.[0-3]
05000189 False Protection Exceptions BF533-0.[0-3]
BF561-0.[0-3]
05000190 PPI not functional at core voltage < 1Volt BF561-0.[0-6]
05000193 False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed BF533-0.[0-3]
BF538-0.[0-5]
BF539-0.[0-5]
BF561-0.[0-3]
05000194 Restarting SPORT in Specific Modes May Cause Data Corruption BF533-0.[0-3]
BF561-0.[0-3]
05000198 Failing MMR Accesses When Stalled by Preceding Memory Read BF533-0.[0-4]
BF561-0.[0-3]
05000199 Current DMA Address Shows Wrong Value During Carry Fix BF533-0.[0-3]
BF538-0.[0-3]
BF539-0.[0-3]
BF561-0.[0-3]
05000200 SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions BF533-0.[3-4]
BF561-0.[2-3]
05000201 Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode BF533-0.3
05000202 Possible Infinite Stall with Specific Dual-DAG Situation BF533-0.[0-4]
BF561-0.[0-3]
05000203 Specific Sequence That Can Cause DMA Error or DMA Stopping BF533-0.[0-3]
05000204 Incorrect data read with write-through cache and allocate cache lines on reads only mode BF533-0.[0-3]
BF561-0.[0-3]
05000205 Specific sequence that can cause DMA error or DMA stopping BF561-0.[0-3]
05000207 Recovery from “Brown-Out” Condition BF533-0.[0-3]
BF561-0.[0-3]
05000208 VSTAT Status Bit in PLL_STAT Register Is Not Functional BF533-0.[0-6]
BF561-0.[0-6]
05000209 Speed Path in Computational Unit Affects Certain Instructions BF533-0.[0-3]
BF561-0.[0-3]
05000215 UART TX Interrupt Masked Erroneously BF533-0.[0-4]
BF561-0.[0-3]
05000219 NMI Event at Boot Time Results in Unpredictable State BF533-0.[0-6]
BF538-0.[0-5]
BF539-0.[0-5]
BF561-0.[0-3]
05000220 Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory BF561-0.[0-3]
05000225 Incorrect Pulse-Width of UART Start Bit BF533-0.[0-4]
BF561-0.[0-3]
05000227 Scratchpad Memory Bank Reads May Return Incorrect Data BF533-0.[0-4]
BF561-0.[0-3]
05000229 SPI Slave Boot Mode Modifies Registers from Reset Value BF533-0.[0-6]
BF538-0.[0-5]
BF539-0.[0-5]
05000230 UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions BF533-0.[0-4]
BF561-0.[0-3]
05000231 UART STB Bit Incorrectly Affects Receiver Setting BF533-0.[0-4]
BF561-0.[0-3]
05000232 SPORT data transmit lines are incorrectly driven in multichannel mode BF561-0.[0-3]
05000233 PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes BF533-0.{0,1,2,3,5}
BF538-0.[0-5]
BF539-0.[0-5]
05000234 Incorrect Revision Number in DSPID Register BF533-0.4
05000242 DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset BF533-0.[0-4]
BF561-0.[0-3]
05000244 If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures BF533-0.[0-4]
BF537-0.[0-2]
BF538-0.[0-1]
BF539-0.[0-1]
BF561-0.[0-3]
05000245 False Hardware Error from an Access in the Shadow of a Conditional Branch BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF533-0.[0-6]
BF537-0.[0-3]
BF538-0.[0-5]
BF539-0.[0-5]
BF548-0.{0,1,2,3M}
BF561-0.[0-5]
05000246 Data CPLBs Should Prevent Spurious Hardware Errors BF533-0.[0-4]
05000248 TESTSET operation forces stall on the other core BF561-0.[0-3]
05000250 Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions BF533-0.4
BF537-0.[0-2]
BF561-0.3
05000251 Exception Not Generated for MMR Accesses in Reserved Region BF561-0.[0-3]
05000252 EMAC Tx DMA error after an early frame abort BF537-0.[0-2]
05000253 Maximum External Clock Speed for Timers BF533-0.[0-4]
BF537-0.[0-2]
BF538-0.[0-5]
BF539-0.[0-5]
BF561-0.[0-3]
05000254 Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF533-0.[5-6]
BF537-0.3
BF561-0.[4-5]
05000255 Entering Hibernate State with RTC Seconds Interrupt Not Functional BF533-0.[0-4]
BF537-0.[0-2]
05000256 EMAC MDIO input latched on wrong MDC edge BF537-0.[0-2]
05000257 Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches BF533-0.[0-4]
BF537-0.[0-2]
BF561-0.[0-4]
05000258 Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ BF533-0.[0-4]
BF537-0.[0-2]
BF561-0.[0-4]
05000260 ICPLB_STATUS MMR Register May Be Corrupted BF533-0.[0-4]
BF537-0.2
BF561-0.[0-4]
05000261 DCPLB_FAULT_ADDR MMR Register May Be Corrupted BF533-0.[0-4]
BF537-0.[0-2]
BF538-0.[0-2]
BF539-0.[0-2]
BF561-0.[0-4]
05000262 Stores To Data Cache May Be Lost BF533-0.[0-4]
BF537-0.[0-2]
BF561-0.[0-4]
05000263 Hardware Loop Corrupted When Taking an ICPLB Exception BF533-0.[0-4]
BF537-0.2
BF561-0.[0-4]
05000264 CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop BF533-0.[0-4]
BF537-0.[0-2]
BF561-0.[0-4]
05000265 Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF533-0.[0-6]
BF537-0.[0-3]
BF548-0.{0,1,2,3M}
BF561-0.[0-5]
05000266 IMDMA destination IRQ status must be read prior to using IMDMA BF561-0.[4-6]
05000267 IMDMA may corrupt data under certain conditions BF561-0.[0-6]
05000268 Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD BF537-0.[0-2]
05000269 High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase BF533-0.[0-4]
BF561-0.[0-4]
05000270 High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease BF533-0.[0-4]
BF537-0.[0-2]
BF538-0.[0-3]
BF539-0.[0-3]
BF561-0.[0-4]
05000271 Spontaneous Reset of Internal Voltage Regulator BF533-0.3
05000272 Certain Data Cache Writethrough Modes Fail for Vddint ⇐ 0.9V BF533-0.[0-6]
BF537-0.[0-4]
BF538-0.[0-5]
BF548-0.{0,1,2,3M}
BF561-0.[0-6]
05000273 Writes to Synchronous SDRAM Memory May Be Lost BF533-0.[0-5]
BF537-0.[0-2]
BF538-0.[0-3]
BF539-0.[0-3]
05000274 Data cache write back to external synchronous memory may be lost BF561-0.[0-6]
05000275 PPI Timing and Sampling Information Updates BF561-0.{0,1,3,4,5,6}
05000276 Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY BF533-0.[0-6]
BF561-0.[0-6]
05000277 Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt BF533-0.[0-5]
BF537-0.[0-2]
BF538-0.[0-3]
BF539-0.[0-3]
BF561-0.[0-4]
05000278 Disabling Peripherals with DMA Running May Cause DMA System Instability BF533-0.[0-5]
BF537-0.[0-2]
BF538-0.[0-3]
BF539-0.[0-3]
BF561-0.[0-4]
05000280 SPI Master boot mode does not work well with Atmel Data flash devices BF537-0.[0-4]
05000281 False Hardware Error Exception When ISR Context Is Not Restored BF533-0.[0-5]
BF537-0.[0-2]
BF538-0.[0-3]
BF539-0.[0-3]
BF548-0.0
BF561-0.[0-4]
05000282 Memory DMA Corruption with 32-Bit Data and Traffic Control BF533-0.[0-5]
BF537-0.[0-2]
BF538-0.[0-3]
BF539-0.[0-3]
05000283 System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage BF533-0.[0-5]
BF537-0.[0-2]
BF538-0.[0-3]
BF539-0.[0-3]
BF561-0.[0-5]
05000285 New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) BF537-0.[0-2]
05000287 A read will receive incorrect data under certain conditions BF561-0.[0-4]
05000288 SPORTs May Receive Bad Data If FIFOs Fill Up BF533-0.[0-5]
BF537-0.[0-2]
BF538-0.[0-3]
BF539-0.[0-3]
BF561-0.[0-4]
05000294 Timer Pin Limitations for PPI TX Modes with External Frame Syncs BF538-0.[0-5]
BF539-0.[0-5]
05000301 Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space BF533-0.[0-5]
BF537-0.[0-4]
BF538-0.[0-3]
BF539-0.[0-3]
BF561-0.[0-6]
05000302 SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly BF533-0.[0-4]
BF561-0.[0-6]
05000304 SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly BF537-0.[0-2]
BF538-0.[0-3]
BF539-0.[0-3]
BF548-0.0
05000305 SPORT_HYS Bit in PLL_CTL Register Is Not Functional BF533-0.[0-4]
BF537-0.[0-2]
BF561-0.[0-4]
05000306 New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) BF533-0.[0-4]
05000307 SCKELOW Bit Does Not Maintain State Through Hibernate BF533
BF537-0.[0-2]
BF538-0.[0-3]
BF539-0.[0-3]
BF561-0.[0-4]
05000309 Writing UART_THR while UART clock is disabled sends erroneous start bit BF537-0.2
05000310 False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF533-0.[0-6]
BF537-0.[0-3]
BF538-0.[0-5]
BF539-0.[0-5]
BF548-0.{0,1,2,3M}
BF561-0.[0-5]
05000311 Erroneous Flag (GPIO) Pin Operations under Specific Sequences BF533-0.[0-5]
05000312 Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted BF533-0.[0-5]
BF537-0.[0-3]
BF538-0.[0-4]
BF539-0.[0-4]
BF548-0.0
BF561-0.[0-5]
05000313 PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes BF526(C)-0.0
BF527(C)-0.[0-1]
BF533-0.[0-5]
BF537-0.[0-3]
BF538-0.[0-3]
BF539-0.[0-3]
BF561-0.[0-5]
05000315 Killed System MMR Write Completes Erroneously On Next System MMR Access BF533-0.[0-5]
BF537-0.[0-2]
BF538-0.[0-3]
BF539-0.[0-3]
BF561-0.[0-5]
05000316 EMAC RMII mode: collisions occur in Full Duplex mode BF537-0.[0-2]
05000319 Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages BF533-0.[0-5]
05000320 PF2 Output Remains Asserted After SPI Master Boot BF561-0.[4-6]
05000321 EMAC RMII mode: TX frames in half duplex fail with status No Carrier BF537-0.[0-2]
05000322 EMAC RMII mode at 10-Base-T speed: RX frames not received properly BF537-0.[0-3]
05000323 Erroneous GPIO Flag Pin Operations Under Specific Sequences BF561-0.[0-5]
05000326 SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits BF561-0.[5-6]
05000328 Incorrect Access of OTP_STATUS During otp_write() Function BF527(C)-0.[0-1]
BF548-0.0
05000330 Host DMA Boot Modes Are Not Functional BF527(C)-0.[0-1]
BF548-0.0
05000331 New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) BF561-0.[0-4]
05000332 New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) BF561-0.[0-4]
05000333 Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status BF561-0.[0-4]
05000337 Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port BF527(C)-0.[0-1]
BF548-0.0
05000339 New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) BF561-0.[0-4]
05000341 Ethernet MAC MDIO Reads Do Not Meet IEEE Specification BF527(C)-0.[0-1]
BF537-0.3
05000342 TWI May Not Operate Correctly Under Certain Signal Termination Conditions BF527(C)-0.[0-1]
05000343 Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory BF561-0.3
05000346 USB Calibration Value Is Not Initialized BF526(C)-0.0
BF527(C)-0.[0-1]
BF548-0.0
05000347 Preboot Routine Incorrectly Alters Reset Value of USB Register BF527(C)-0.[0-1]
BF548-0.0
05000348 Security Features Are Not Functional BF527(C)-0.0
05000350 New Feature: UART Remains Enabled after UART Boot BF537-0.[0-2]
05000353 bfrom_SysControl() Firmware Function Performs Improper System Reset BF526(C)-0.0
BF548-0.[0-1]
05000355 Regulator Programming Blocked when Hibernate Wakeup Source Remains Active BF527(C)-0.[0-1]
BF537-0.[0-3]
BF538-0.[0-4]
BF539-0.[0-4]
BF548-0.0
05000357 Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled BF527(C)-0.[0-1]
BF533-0.[0-5]
BF537-0.[0-3]
BF538-0.[0-4]
BF539-0.[0-4]
BF548-0.{0,1,2,3M}
BF561-0.[0-5]
05000359 DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked BF537-0.[0-4]
05000360 External Memory Read Access Hangs Core With PLL Bypass BF548-0.{0,1,2,3M}
05000362 Conflicting Column Address Widths Causes SDRAM Errors BF561-0.[0-6]
05000363 UART Break Signal Issues BF533-0.[0-4]
BF561-0.[0-3]
05000364 Incorrect Revision Number in DSPID Register BF527(C)-0.1
05000365 DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked BF548-0.{0,1,2,3M}
05000366 PPI Underflow Error Goes Undetected in ITU-R 656 Mode BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF533-0.[0-6]
BF537-0.[0-3]
BF538-0.[0-5]
BF539-0.[0-5]
BF561-0.[0-5]
05000368 Incorrect Default CSEL Value in PLL_DIV BF527(C)-0.[0-1]
05000369 Addressing Conflict between Boot ROM and Asynchronous Memory BF548-0.{0,1,2,3M}
05000371 Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration BF527(C)-0.[0-1]
BF533-0.[0-5]
BF537-0.[0-3]
BF538-0.[0-4]
BF539-0.[0-4]
BF548-0.[0-1]
BF561-0.[0-5]
05000374 Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current BF538-0.4
BF539-0.4
05000376 Authentication Fails To Initiate BF527(C)-0.[0-1]
05000380 Data Read From L3 Memory by USB DMA May be Corrupted BF527(C)-0.[0-1]
05000382 8-Bit NAND Flash Boot Mode Not Functional BF526(C)-0.0
BF527(C)-0.[0-1]
BF548-0.0
05000383 Some ATAPI Modes Are Not Functional BF548-0.{0,1,2,3M}
05000385 Boot from OTP Memory Not Functional BF527(C)-0.[0-1]
BF548-0.0
05000386 bfrom_SysControl() Firmware Routine Not Functional BF527(C)-0.[0-1]
BF548-0.0
05000387 Programmable Preboot Settings Not Functional BF527(C)-0.[0-1]
BF548-0.0
05000388 CRC32 Checksum Support Not Functional BF526(C)-0.0
BF527(C)-0.[0-1]
BF548-0.0
05000389 Reset Vector Must Not Be in SDRAM Memory Space BF527(C)-0.[0-1]
BF548-0.0
05000392 pTempCurrent Not Present in ADI_BOOT_DATA Structure BF527(C)-0.[0-1]
BF548-0.0
05000393 Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure BF527(C)-0.[0-1]
BF548-0.0
05000394 Log Buffer Not Functional BF527(C)-0.[0-1]
BF548-0.0
05000395 Hook Routine Not Functional BF527(C)-0.[0-1]
BF548-0.0
05000396 Header Indirect Bit Not Functional BF527(C)-0.[0-1]
BF548-0.0
05000397 BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional BF527(C)-0.[0-1]
BF548-0.0
05000398 SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional BF527(C)-0.[0-1]
05000399 BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional BF527(C)-0.[0-1]
05000400 PPI Does Not Start Properly In Specific Mode BF533-0.5
05000401 PPI Data Signals D0 and D8 do not Tristate After Disabling PPI BF526(C)-0.0
BF527(C)-0.[0-1]
05000402 SSYNC Stalls Processor when Executed from Non-Cacheable Memory BF533-0.5
BF537-0.2
BF538-0.3
BF539-0.3
05000403 Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall BF526(C)-0.0
BF527(C)-0.[0-1]
BF533-0.[0-6]
BF537-0.[0-3]
BF538-0.[0-5]
BF539-0.[0-5]
BF561-0.[0-5]
05000404 Lockbox SESR Disallows Certain User Interrupts BF526(C)-0.0
BF527(C)-0.[0-1]
BF548-0.[0-1]
05000405 Lockbox SESR Firmware Does Not Save/Restore Full Context BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF548-0.{0,1,2,3M}
05000407 Lockbox SESR Firmware Arguments Are Not Retained After First Initialization BF526(C)-0.0
BF527(C)-0.[0-1]
BF548-0.[0-1]
05000408 Lockbox Firmware Memory Cleanup Routine Does not Clear Registers BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF548-0.{0,1,2,3M}
05000409 Lockbox firmware leaves MDMA0 channel enabled BF526(C)-0.0
BF527(C)-0.[0-1]
BF548-0.[0-1]
05000410 Incorrect Default Internal Voltage Regulator Setting BF527(C)-0.[0-1]
05000411 bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes BF526(C)-0.0
BF548-0.[0-1]
05000412 TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled BF561-0.[0-5]
05000414 OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API BF526(C)-0.0
BF527(C)-0.[0-1]
BF548-0.[0-1]
05000415 DEB2_URGENT Bit Not Functional BF526(C)-0.0
BF527(C)-0.[0-1]
05000416 Speculative Fetches Can Cause Undesired External FIFO Operations BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF533-0.[0-6]
BF537-0.[0-3]
BF538-0.[0-5]
BF539-0.[0-5]
BF548-0.{0,1,2,3M}
BF561-0.[0-5]
05000417 SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output BF527(C)-0.[0-1]
05000418 PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications BF526(C)-0.0
BF527(C)-0.[0-1]
05000420 USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status BF526(C)-0.0
BF527(C)-0.[0-1]
05000421 TWI Fall Time (Tof) May Violate the Minimum I2C Specification BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
05000422 TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification BF518(F)-0.[0-1]
BF526(C)-0.1
BF527(C)-0.2
05000423 Certain Ethernet Frames With Errors are Misclassified in RMII Mode BF526(C)-0.0
BF527(C)-0.[0-1]
05000424 Internal Voltage Regulator Not Trimmed BF527(C)-0.[0-1]
05000425 Multichannel SPORT Channel Misalignment Under Specific Configuration BF526(C)-0.0
BF527(C)-0.[0-1]
BF533-0.[0-6]
BF537-0.[0-3]
BF538-0.[0-5]
BF539-0.[0-5]
BF548-0.{0,1,2,3M}
BF561-0.[0-5]
05000426 Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF533-0.[0-6]
BF537-0.[0-3]
BF538-0.[0-5]
BF539-0.[0-5]
BF548-0.{0,1,2,3M}
BF561-0.[0-5]
05000428 Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B BF561-0.[4-5]
05000429 WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status BF526(C)-0.0
BF527(C)-0.[0-1]
BF548-0.[0-1]
05000430 Software System Reset Corrupts PLL_LOCKCNT Register BF518(F)-0.0
BF527(C)-0.2
BF548-0.2
05000431 Incorrect Use of Stack in Lockbox Firmware During Authentication BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF548-0.[0-2]
05000432 bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence BF526(C)-0.0
05000435 Certain SIC Registers are not Reset After Soft or Core Double Fault Reset BF518(F)-0.0
BF526(C)-0.0
BF527(C)-0.[0-2]
05000436 Specific GPIO Pins May Change State when Entering Hibernate BF538-0.[4-5]
BF539-0.[4-5]
05000438 PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values BF518(F)-0.0
05000439 Preboot Cannot be Used to Alter the PLL_DIV Register BF518(F)-0.0
BF526(C)-0.0
BF527(C)-0.[0-2]
05000440 bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register BF518(F)-0.0
BF526(C)-0.0
BF527(C)-0.[0-2]
05000442 OTP Write Accesses Not Supported BF527(C)-0.0
BF548-0.0
05000443 IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall BF518(F)-0.[0-1]
BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF533-0.[0-6]
BF537-0.[0-3]
BF538-0.[0-5]
BF539-0.[0-5]
BF548-0.{0,1,2,3M}
BF561-0.[0-5]
05000444 Incorrect L1 Instruction Bank B Memory Map Location BF518(F)-0.0
05000445 The WURESET Bit in the SYSCR Register is not Functional BF527(C)-0.[0-2]
05000446 CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional BF548-0.{0,1,2,3M}
05000447 UART IrDA Receiver Fails on Extended Bit Pulses BF548-0.{0,1,2,3M}
05000450 USB DMA Mode 1 Short Packet Data Corruption BF548-0.{0,1,2,3M}
05000451 BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional BF527(C)-0.[0-2]
05000452 Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals BF518(F)-0.0
BF526(C)-0.0
BF527(C)-0.[0-2]
05000453 PWM_TRIPB Signal Not Available on PG10 BF518(F)-0.0
05000455 PPI_FS3 is Driven One Half Cycle Later Than PPI Data BF518(F)-0.0
05000456 USB Receive Interrupt Is Not Generated in DMA Mode 1 BF526(C)-0.[0-1]
BF527(C)-0.[0-2]
BF548-0.{0,1,2,3M}
05000457 Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion BF526(C)-0.[0-1]
BF527(C)-0.[0-2]

Anomalies with no planned Workarounds

Since many anomalies are fixed on early silicon, it is normally the plan of the team working on the GNU Toolchain, and the Linux kernel not to implement workarounds which are early (0.0) or no longer avalible (too old). This is that list:

This list is autogenerated - DO NOT EDIT

Anomaly Summary Blackfin Workaround in
ID affected Hardware Toolchain U-Boot Linux Kernel
05000066 Internal voltage regulator can't be modified via register writes BF533-0.0
BF533-0.1
05000067 Watchpoints (Hardware Breakpoints) are not supported BF533-0.[0-2]
05000070 SDRAM PSSE bit cannot be set again after SDRAM Powerup BF533-0.0
BF533-0.1
05000079 Writing FIO_DIR can corrupt a programmable flag's data BF533-0.[0-1]
05000086 Timer Auto-Baud Mode requires the UART clock to be enabled BF533-0.0
BF533-0.1
05000088 Internal Clocking Modes on SPORT0 not supported BF533-0.[0-1]
05000092 Internal voltage regulator does not wake up from an RTC wakeup BF533-0.0
BF533-0.1
05000093 The IFLUSH instruction must be preceded by a CSYNC instruction BF533-0.[0-1]
05000095 Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior BF533-0.[0-1]
05000096 PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC BF533-0.[0-1]
05000097 Performance Monitor 0 and 1 are swapped when monitoring memory events BF533-0.0
BF533-0.1
05000098 32-bit SPORT DMA will be word reversed BF533-0.[0-1]
05000100 Incorrect status in the UART_IIR register BF533-0.0
BF533-0.1
05000101 Reading X_MODIFY or Y_MODIFY while DMA channel is active BF533-0.0
BF533-0.1
05000102 Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers BF533-0.[0-1]
05000103 Incorrect value written to the cycle counters BF533-0.[0-1]
05000104 Stores to L1 Data memory incorrect when a specific sequence is followed BF533-0.[0-1]
05000106 Programmable Flag (PF3) functionality not supported in all PPI modes BF533-0.[0-1]
05000107 Data store can be lost when targeting a cache line fill BF533-0.[0-1]
05000109 Reserved bits in SYSCFG register not set at power on BF533-0.[0-2]
05000114 Infinite Core Stall BF533-0.[0-1]
05000115 PPI_FSx may glitch when generated by the on chip Timers BF533-0.0
BF533-0.1
05000116 Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers BF533-0.[0-2]
BF561-0.[0-2]
05000117 DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 BF533-0.[0-1]
05000118 Booting from an 8-bit or 24-bit Addressable SPI device is not supported BF533-0.[0-1]
05000123 DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active BF533-0.[0-2]
05000124 DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 BF533-0.[0-2]
05000125 Erroneous exception when enabling cache BF533-0.[0-2]
BF561-0.[0-2]
05000126 SPI clock polarity and phase bits incorrect during booting BF533-0.[1-2]
05000134 Two bits in the Watchpoint Status Register (WPSTAT) are swapped BF561-0.2
05000135 Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped BF561-0.2
05000136 Stall in multi-unit DMA operations BF561-0.[0-2]
05000137 DMEM_CONTROL is not set on Reset BF533-0.[0-2]
05000138 SPI boot will not complete if there is a zero fill block in the loader file BF533-0.2
05000139 Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs BF533-0.[0-1]
05000140 Allowing the SPORT RX FIFO to fill will cause an overflow BF533-0.[0-2]
BF561-0.[0-2]
05000141 An Infinite Stall occurs with a particular sequence of consecutive dual dag events BF533-0.[0-2]
BF561-0.[0-2]
05000142 Interrupts may be lost when a programmable input flag is configured to be edge sensitive BF533-0.[0-2]
BF561-0.[0-2]
05000143 A read from external memory may return a wrong value with data cache enabled BF533-0.[0-2]
05000144 DMA and TESTSET conflict when both are accessing external memory BF533-0.[0-2]
BF561-0.[0-2]
05000145 In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK BF533-0.[0-2]
BF561-0.[0-2]
05000146 MDMA may lose the first few words of a descriptor chain BF533-0.[0-2]
BF561-0.[0-2]
05000147 Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch BF533-0.[0-2]
BF561-0.[0-2]
05000148 When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 BF533-0.[0-2]
05000150 DMA engine may lose data due to incorrect handshaking BF561-0.[0-2]
05000151 DMA stalls when all three controllers read data from the same source BF561-0.[0-2]
05000152 Execution stall when executing in L2 and doing external accesses BF561-0.[0-2]
05000153 Frame Delay in SPORT Multichannel Mode BF533-0.[0-2]
BF561-0.[0-2]
05000154 SPORT TFS signal stays active in multichannel mode outside of valid channels BF533-0.[0-2]
BF561-0.[0-2]
05000155 Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use BF533-0.[0-2]
05000157 Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit BF533-0.[0-2]
BF537-0.[0-1]
BF561-0.[0-2]
05000159 DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 BF561-0.[0-2]
05000160 A read from external memory may return a wrong value with data cache enabled BF561-0.[0-2]
05000161 Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist BF561-0.[0-2]
05000162 DMEM_CONTROL<12> is not set on Reset BF561-0.[0-2]
05000163 SPORT transmit data is not gated by external frame sync in certain conditions BF533-0.[0-2]
BF561-0.[0-2]
05000172 DSPID register values incorrect BF561-0.2
05000173 DMA vs Core accesses to external memory BF533-0.[0-2]
BF561-0.[0-2]
05000191 PPI does not invert the Driving PPICLK edge in Transmit Modes BF533-0.[0-2]
BF561-0.[0-2]
05000192 In PPI Transmit Modes with External Frame Syncs POLC BF533-0.[0-2]
05000206 Internal Voltage Regulator may not start up BF533-0.[0-2]
05000237 Instruction Cache Is Not Functional BF537-0.[0-1]
05000247 CLKIN Buffer Output Enable Reset Behavior Is Changed BF537-0.[0-1]
05000291 Reads from CAN Mailbox and Acceptance Mask Area Can Fail BF538-0.[0-3]
BF539-0.[0-3]
05000293 Hibernate Leakage Current Is Higher Than Specified BF538-0.[0-3]
BF539-0.[0-3]
05000318 PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T BF539-0.[0-3]
05000324 TWI Slave Boot Mode Is Not Functional BF548-0.0
05000325 External FIFO Boot Mode Is Not Functional BF548-0.[0-1]
05000327 Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously BF548-0.0
05000329 Synchronous Burst Flash Boot Mode Is Not Functional BF548-0.0
05000334 Inadequate Timing Margins on DDR DQS to DQ and DQM Skew BF548-0.0
05000335 Inadequate Rotary Debounce Logic Duration BF548-0.0
05000336 Phantom Interrupt Occurs After First Configuration of Host DMA Port BF548-0.0
05000338 Slave-Mode SPI0 MISO Failure With CPHA = 0 BF548-0.0
05000340 If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read BF548-0.0
05000344 Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped BF548-0.0
05000346_value USB Calibration Value to use BF52[67]
BF548
05000349 Data Lost when Core Reads SDH Data FIFO BF548-0.0
05000351 PLL Status Register Is Inaccurate BF548-0.0
05000356 System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required BF548-0.0
05000367 WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up BF548-0.0
05000370 Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications BF548-0.0
05000372 USB DP/DM Data Pins May Lose State When Entering Hibernate BF548-0.0
05000375 New Feature: Open-Drain GPIO Outputs on PC1 and PC4 (Not Available on Older Silicon) BF538-0.[0-3]
BF539-0.[0-3]
05000378 Security/Authentication Speedpath Causes Authentication To Fail To Initiate BF548-0.[0-1]
05000379 16-Bit NAND FLASH Boot Mode Is Not Functional BF548-0.[0-1]
05000390 Changed Meaning of BCODE Field in SYSCR Register BF548-0.0
05000391 Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail BF548-0.0
05000406 Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range BF548-0.[0-1]
05000413 NAND Boot Mode Not Compatible With Some NAND Flash Devices BF548-0.[0-1]
05000427 CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional BF548-0.[0-1]
05000448 DDR Clock Duty Cycle Spec Violation (tCH, tCL) BF548-0.1
05000449 Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) BF548-0.1
05000461 False Hardware Error when RETI points to invalid memory BF518
BF52[67]
BF533
BF537
BF53[89]
BF548
BF561