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Anomaly Workarounds in Das U-Boot

Silicon anomalies can lead to erratic behaviors and consequently lead to instability in a hardware system. This document outlines all the silicon anomaly workarounds relevant to Das U-Boot, targeting the Blackfin processors.

Please keep this list sorted numerically.

05000099

Description

The UART Line Status Register (UART_LSR) bits are not updated at the same time. Direct Polling of the UART_LSR register may miss any of the Line Status conditions.

Workaround

file: arch/blackfin/cpu/serial.c

scm failed with exit code 1:
file does not exist in git

05000158

Description

After a DMA or core MMR DTEST register access has occurred to the L1 instruction memory, a data cache fill to the corresponding port may get corrupted data. This situation can only occur if stalls are introduced because the core is accessing the same data memory bank as the data cache fill.

This data cache fill can occur many cycles after the L1 Instruction memory DMA or MMR access. One example of the failure is when a program that enables data cache is booted. The Instruction DMA that occurred during the boot may prime the processor to be susceptible to data corruption in a data cache fill that occurs sometime during the main program's execution. For Port A, data locations 0xFF80xxxx and instruction locations 0xFFA00000 -0xFFA07FFF (where applicable) are subject to the failure. For Port B, data locations 0xFF90xxxx and instruction locations 0xFFA08000 - 0xFFA0FFFF (where applicable) are subject to the failure. The problem will also occur if the last DMA transaction was to the L1 instruction memory while a low priority data cache fill is ongoing.

Workaround

The best workaround for this issue is to set bit 9 of any DCPLB Data register that is used.

file: arch/blackfin/include/asm/cplb.h

scm failed with exit code 1:
file does not exist in git

file: arch/blackfin/include/asm/cplb.h

scm failed with exit code 1:
file does not exist in git